Senior Photolithography Process Engineer

NXP Semiconductors

📍Chandler, AZ
Posted May 19, 2026

Job Overview

Position

Senior Photolithography Process Engineer

Company

NXP Semiconductors

Location

Chandler, AZ

Work Type

On-site

Job ID

li-4407549978

Job Description

Business Line Description
NXP’s Front End Operations plays an essential role in the company’s success by ensuring manufacturing excellence and delivery of high quality, scalable, and cost-competitive semiconductor devices to create a winning advantage for our customers.

Job Summary
Photolithography Process Engineer in a high-volume semiconductor wafer manufacturing environment. Prior experience with semiconductor manufacturing process is required. Previous experience with ASML Scanner, Canon Stepper, TEL ACT 8 or Mark 7 track, KLA 8100 CDSEM or Archers is highly desirable.

Key Challenges

  • Reducing overall cost of non-conformal like wafer scrap, and photo rework

  • Developing and writing standard work procedure document for Out of Control Action Plan

  • Implementation of process SPC using Six-Sigma statistical methodology

  • Process development and optimization utilizing Six-Sigma methodology

  • Improving tool utilization and availability

  • Working with manufacturing and industrial engineering for capacity planning and modeling

  • Participating in and/or leading cross-functional and lean activity teams

  • Supporting process development activities

  • Sourcing and process releasing new equipment

  • Training process technician in dispositioning of wafer in process out of control situations

  • Training wafer FAB associate in process tool operation using our standard work process

Cross Functional Aspects

  • Working closely with Photo equipment team to identify and reduce source of process variation and implementing zero defect process

  • Collaborate with device team to improve process integration margin

Job Qualifications

  • Must have a BS or MS degree in engineering or a degree in relevant field of studies

  • More than 5 years of process engineering experience in a similar high volume semiconductor manufacturing environment is preferred

  • Six-Sigma statistical methodology

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

Interview Prep

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Key Skills

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Practice Questions

💡Technical Questions (3)
  • 1.How do you approach implementing Statistical Process Control (SPC) for a photolithography process, and what key metrics would you monitor on tools like ASML scanners or TEL tracks?
  • 2.Can you walk me through your methodology for reducing the cost of non-conformal materials, specifically wafer scrap and photo rework, in a high-volume fab?
  • 3.Describe your experience with sourcing and process releasing new photolithography equipment. How do you ensure it meets manufacturing and integration requirements?
🎯Behavioral Questions (3)
  • 1.Tell me about a time you had to train process technicians or fab associates on a new standard work procedure or out-of-control action plan. How did you ensure they understood and followed it?
  • 2.Describe a situation where you worked closely with the photo equipment team to identify and reduce a source of process variation to achieve a zero-defect goal.
  • 3.Give me an example of a time you led or participated in a cross-functional lean activity team to improve tool utilization or capacity planning.
🧩Situational Questions (2)
  • 1.You are notified by manufacturing that the KLA 8100 CDSEM is showing a sudden shift in critical dimension uniformity on a product running on an ASML scanner. Wafers are still in the queue. What are your immediate steps?
  • 2.You are leading a process optimization project using Six-Sigma, but the device engineering team is resistant to your proposed parameter changes because they are concerned it will narrow their integration margin. How do you handle this?

Resume Keywords

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PhotolithographyASML ScannerTEL TrackKLA CDSEMSix-SigmaSPCSemiconductor ManufacturingProcess OptimizationCost ReductionStandard WorkCross-FunctionalEquipment Qualification

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